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HV507 300V, 64-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs
Ordering Information
Package Options Device HV507 Recommended Operating VPP Max* 300V 80-Lead Plastic Gullwing HV507PG Die HV507X
* Please consult factory for higher voltage operation.
Features
HVCMOS(R) technology Operating output voltage of 300V Low power level shifting from 5V to 300V Shift register speed 8MHz @ VDD = 5V 64 latched data outputs Output polarity and blanking CMOS compatible inputs Forward and reverse shifting options
General Description
The HV507 is a low voltage serial to high voltage parallel converter with 64 high voltage push-pull outputs. This device has been designed for use as a printer driver for electrostatic applications. It can also be used in any application requiring multiple high voltage outputs, low current sourcing and sinking capabilities. The device consists of a 64-bit shift register, 64 latches, and control logic to perform the polarity select and blanking of the outputs. A DIR pin controls the direction of data shift through the device. With DIR grounded, DIOA is Data In and DIOB is Data Out; data is shifted from HVOUT64 to HVOUT1. When DIR is at logic high, DIOB is Data In and DIOA is Data Out: data is then shifted from HVOUT1 to HVOUT64. Data is shifted through the shift register on the low to high transition of the clock. Data output buffers are provided for cascading devices. Operation of the shift register is not affected by the LE, BL, or the POL inputs. Transfer of data from the shift register to the latch occurs when the LE is high. The data in the latch is stored during LE transition from high to low.
Absolute Maximum Ratings1
Supply voltage, VDD Supply voltage, VPP Logic input levels Ground current3 current2 dissipation3 -0.5V to +6V VDD to 320V -0.5V to VDD +0.5V 0.5A 0.5A 1200mW 0C to +70C -65C to +150C
High voltage supply
Continuous total power
Operating temperature range Storage temperature range
Notes: 1. All voltages are referenced to GND. 2. Connection to all power and ground pads is required. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25C ambient derate linearly to 70C at 26.7mW/C.
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the 1 Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV507
Electrical Characteristics (for V
DC Characteristics
Symbol IDD IDDQ IPP IIH IIL VOH VOL VOC Parameter VDD supply current Quiescent VDD supply current High voltage supply current
DD
= 5V, VPP = 300V, TA = 250C)
Min Typ Max 15 Units mA Conditions fCLK = 8MHz, fDATA = 4MHz LE = LOW 200 0.50 0.50 A mA mA A A V V 35 1.0 VPP +1.5 -30 V V V V All VIN = 0V or VDD VPP = 300V All outputs high VPP = 300V All outputs low VIH = VDD VIL = 0V VPP = 300V, IHVOUT = -1mA IDOUT = -100A VDD = 5V, IHVOUT = 1mA IDOUT = 100A IOC = 1mA IOC = -1mA
High-level logic input current Low-level logic input current High-level output HVOUT Data out Low-level output HVOUT Data out HVOUT clamp voltage 265 VDD -1V
10 -10
AC Characteristics1 (For VDD = 5V, VPP = 300V, TA = 25C)
Symbol fCLK tW tSU tH tWLE tDLE tSLE tON, tOFF tDHL tDLH tr, tf Clock frequency Clock width high and low Data setup time before clock rises Data hold time after clock rises Width of latch enable pulse LE delay time after rising edge of clock LE setup time before rising edge of clock Time from latch enable to HVOUT Delay time clock to data out high to low Delay time clock to data out low to high All logic inputs 62 35 30 80 35 40 4 125 125 5 Parameter Min Typ Max 8 Units MHz ns ns ns ns ns ns s ns ns ns CL = 20pF CL = 20pF CL = 20pF Conditions
Note: 1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec.
Recommended Operating Conditions
Symbol VDD VPP VIH VIL TA Logic supply voltage High voltage supply High-level input voltage Low-level input voltage Operating free-air temperature Parameter Min 4.5 60 VDD -0.9 0 0 Typ 5.0 Max 5.5 300 VDD 0.9 +70 Units V V V V C
Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. Power-down sequence should be the reverse of the above.
4. Apply VPP. 5. The VPP should not drop below VDD or float during operation.
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HV507
Input and Output Equivalent Circuits
VDD VDD VPP
Input
Data Out
HVOUT
GND Logic Inputs
GND Logic Data Output
HVGND High Voltage Outputs
Switching Waveforms
VIH Data In (DIOA/DIOB) 50% tSU CLK 50% tWL 50% tWH 50% VOL Data Out (D IOA/D IOB) tDLH 50% tDHL VOH VOL Data Valid tH VIH 50% 50% VIL VOH 50% VIL
LE tDLE
50% tWLE
50% tSLE
VIH VOL
HV OUT w/ S/R LOW tOFF HV OUT w/ S/R HIGH
90% 10%
VOH VOL
10% tON
90%
VOH VOL
3
HV507
Functional Block Diagram
POL BL LE DIOA VPP
L/T
HVOUT1
CLK
L/T
HVOUT2 * * * 60 Additional Outputs * * * HVOUT63
DIR
64-bit Static Shift Register
64 Latches
L/T
L/T
HVOUT64
DIOB
L/T = Level Translator
Function Table
Inputs Function Data X X X H or L X X L H DIOA DIOB CLK X X X X X LE X X L L H H X X BL L L H H H H H H X X POL L H L H H L H H X X DIR X X X X X X X X L H Shift Reg 1 All on All off Invert mode Load S/R Store data in latches Transparent latch mode I/O relation * * * 2...64 *...* *...* *...* 1 H L * * * * L H -- -- Outputs HV Outputs 2...64 H...H L...L *...* *...* *...* *...* *...* *...* Data Out * * * * * * * * * DIOB DIOA
H or L *...* * * L H Qn Qn *...* *...* *...* *...* Qn-1 Qn+1
Notes: H = high level, L = low level, X = irrelevant, = low-to-high transition, = high-to-low transition. * = dependent on previous stage's state before the last CLK or last LE high.
4
HV507
Pin Configurations
HV507 80 Pin Gullwing Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function HVOUT 41 HVOUT 42 HVOUT 43 HVOUT 44 HVOUT 45 HVOUT 46 HVOUT 47 HVOUT 48 HVOUT 49 HVOUT 50 HVOUT 51 HVOUT 52 HVOUT 53 HVOUT 54 HVOUT 55 HVOUT 56 HVOUT 57 HVOUT 58 HVOUT 59 HVOUT 60 HVOUT 61 HVOUT 62 HVOUT 63 HVOUT 64 VPP DIOA N/C N/C BL POL VDD DIR GND HVGND N/C N/C CLK LE DIOB VPP Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function HVOUT 1 HVOUT 2 HVOUT 3 HVOUT 4 HVOUT 5 HVOUT 6 HVOUT 7 HVOUT 8 HVOUT 9 HVOUT 10 HVOUT 11 HVOUT 12 HVOUT 13 HVOUT 14 HVOUT 15 HVOUT 16 HVOUT 17 HVOUT 18 HVOUT 19 HVOUT 20 HVOUT 21 HVOUT 22 HVOUT 23 HVOUT 24 HVOUT 25 HVOUT 26 HVOUT 27 HVOUT 28 HVOUT 29 HVOUT 30 HVOUT 31 HVOUT 32 HVOUT 33 HVOUT 34 HVOUT 35 HVOUT 36 HVOUT 37 HVOUT 38 HVOUT 39 HVOUT 40
Package Outline
64 41
65
40
Index
80
25
1
24
top view
80-pin Gullwing Package
12/13/010
(c)2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
5
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com

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